ESD Reliability Challenges for RF/Mixed Signal Design & Processing

It is forecasted that by 2003, a large number of applications will use CMOS technology for RF system-on-chip, such as remote control, radio modems, home system automation, etc. For example, in the home system automation, the concept is to replace the data cable between appliances by wireless link centered at 2.4GHz, with a range of approximately 8m. The reliability of the components used in these applications is, therefore, obviously very important. Further, rapid progress in Silicon technologies results in additional set of constraints (mostly) and occasionally beneficial solutions. Harnessing the reliability without sacrificing the performance in the deep submicron CMOS technology is of major emphasis in the semiconductor industry. In this tutorial, the ESD reliability challenges faced from technology generations, as well as, circuit design point of view are reviewed. After a brief introduction on the fundamental of electrostatic discharge, detailed description on the ESD testing and models are presented. This intended to provide an in-depth insight into the ESD models, physical and circuit equivalents, relevant international testing standards and procedures for beginners and experts. Novel testing methods for effective device characterization/parameter extraction for circuit level simulation is highlighted. This is a key learning step for circuit designers as such a inter-disciplinary topic is of high interest since it can link the physical failures to circuit simulation. This is followed by a review on the basic on-chip ESD protection building blocks in terms of stand-alone devices and integrated protection circuit schemes. In this section, the ESD specific behavior and application of various standard protection devices such as resistors, diodes, grounded gate nMOST, etc. are explained. Influence of the silicon process and scaling is discussed along with device optimization specific for ESD performance. In the second part of the tutorial, extensive in-depth overview on the entire spectrum of ESD protection circuit design for various technologies such as CMOS and BiCMOS is presented. Brief historical perspective is provided as an introduction, most of which are still practiced in the industry to achieve excellent ESD performance. The basic and advanced concepts involved in designing an ESD protection circuit using the stand-alone devices described in the preceding section are presented. Some typical examples are provided for common applications. This section also outlines various issues in mixed signal applications, such as multiple power supply voltage, above the rail signal pins, etc., and issues pertaining to Charged Device model ESD events. A brief introduction into the device and circuit simulation methodologies is then presented. The purpose of this section is to highlight the possibilities of the modeling and simulation approach as well as to show their usefulness to reduce product development cycle time. A few case studies are provided to demonstrate the usefulness of the ESD simulations (device and circuit level). Due to the stringent load limitations, the success of implementing a robust ESD protection in modern RF CMOS circuits depends on careful selection, design and layout of the devices. Further, at frequencies above 2.5GHz, the design window for application of most of these traditional ESD protection devices rapidly deteriorates. The last section of this tutorial, therefore, highlights the Proceedings of the 16th International Conference on VLSI Design (VLSI’03) 1063-9667/03 $17.00 © 2003 IEEE benefits and limitations of the standard ESD protection methodologies for RF designs. After a clear introduction on the challenges for ESD protection in RF CMOS applications, a thorough overview on the various options for RFCMOS ESD protection is presented. Various reported approaches are compared and the limits of the conventional approach discussed. The possible optimization strategies that could be used to achieve satisfactory ESD performance are outlined. Dr. Natarajan Mahadevan Iyer is working in the Technology, Reliability and Yield group of IMEC, Belgium as Section Leader for the ESD research activities. He received his Ph.D. degree in Solid State Physics and subsequently did post-doctoral work on low temperature device reliability. From 1994 to 2000 he worked as a member of technical staff in the Failure Analysis and Reliability Department, IME, Singapore, and has been involved in the ESD/latch-up research, IC Failure Analysis, and various analytical techniques. His research interests are ESD engineering, device failure physics and analysis, and scanning probe microscopy. He is a Senior Member of IEEE, and member of EDFAS and ESD Association. He has published 25 papers in ICFA, ESD and analytical techniques, and conducted numerous workshops/training sessions on the effects of ESD on microelectronics, ESD issues in GMR/MR heads, ICFA and analytical techniques in USA, Belgium, Singapore and Malaysia. He is also a member of the Device Testing Working Group of the ESD Standards Association, USA, and in the Technical Program Committees of the IEEE IPFA Symposium, 2001-2003, Singapore, EOS/ESD symposium 2002, USA and MRS-ICMAT Symposium 2003, Singapore. Dr. M.K. Radhakrishnan has 25 years experience in the semiconductor device manufacturing, device analysis and quality and reliability studies, at various institutions including avionics research, semiconductor manufacturing and independent R&D laboratories. He is the Principal Consultant for Device Reliability at Philips Electronics Singapore. As a consultant on Microelectronics Device Analysis and Reliability, he has worked with various semiconductor manufacturers (including Philips, Agilent, Infineon, ST Microelectronics, etc.) as well as several bodies including International Telecom Union (ITU), Geneva. He was the Technical Program Chairman for IEEE conferences IPFA ‘95 and IPFA ‘97, and General Chairman for IPFA ‘99 and TPC member of EOS/ESD symposium 2000 and MRS Symposium 2003. Dr. Radhakrishnan is the Editorial Advisory Board Member of Microelectronics Reliability journal (UK) and Editorial board member of Journal of Semiconductor Technology and Science (JSTS). He is an IEEE EDS Distinguished Lecturer in the area of microelectronic device analysis and reliability. Currently he is the IEEE Reliability/CPMT/ED Singapore Chapter Chairman. He is an adjunct faculty in the National University of Singapore. He has designed and conducted a large number (>50) of invited tutorials, workshops and courses at various international conferences on various aspects of IC Device Analysis & Reliability, and has given more than 30 invited talks at various institutions. His current research interests include ultra-thin gate oxide reliability, Cu metallisation and process induced failures in sub-micron devices, EOS/ESD induced failures in devices and building-in reliability in devices. He has more than 40 research publications in the field, including invited papers in IEDM and SPIE conferences. He is a Senior Member of IEEE, Member of ESD Association, USA and Member of EDFAS, USA. Proceedings of the 16th International Conference on VLSI Design (VLSI’03) 1063-9667/03 $17.00 © 2003 IEEE